Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-27
10.3.1.11 Transfer Error Interrupt Enable Register (LTEIR)
The transfer error interrupt enable register (LTEIR), shown in Figure 10-15, is used to send or block
error/event reporting through the eLBC internal interrupt mechanism. Software should clear pending
errors/events in LTESR before enabling interrupts. After an interrupt has occurred, clearing relevant
LTESR error/event bits negates the interrupt.
Table 10-18 describes LTEIR fields.
Offset 0x0_50B8 Access: Read/Write
012 3 456 1112 13 15
R
BMI FCTI PA RI
—
WPI — CSI —
W
Reset All zeros
16 29 30 31
R
— UCCI CCI
W
Reset All zeros
Figure 10-15. Transfer Error Interrupt Enable Register (LTEIR)
Table 10-18. LTEIR Field Descriptions
Bits Name Description
0 BMI Bus monitor error interrupt enable.
0 Bus monitor error reporting is disabled.
1 Bus monitor error reporting is enabled.
1 FCTI FCM command time-out interrupt enable.
0 FCM command time-out error reporting is disabled.
1 FCM command time-out error reporting is enabled.
2 PARI ECC error interrupt enable.
0 ECC error reporting is disabled.
1 ECC error reporting is enabled.
3–4 — Reserved
5 WPI Write protect error interrupt enable.
0 Write protect error reporting is disabled.
1 Write protect error reporting is enabled.
6–11 — Reserved
12 CSI Chip select error interrupt enable.
0 Chip select error reporting is disabled.
1 Chip select error reporting is enabled.
13–29 — Reserved