Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-26 Freescale Semiconductor
10.3.1.10 Transfer Error Check Disable Register (LTEDR)
The transfer error check disable register (LTEDR), shown in Figure 10-14, is used to disable error/event
checking. Note that control of error/event checking is independent of control of reporting of errors/events
(LTEIR) through the interrupt mechanism.
Table 10-17 describes LTEDR fields.
Offset 0x0_50B4 Access: Read/Write
012 3 456 1112 13 15
R
BMD FCTD PARD — WPD — CSD —
W
Reset All zeros
16 29 30 31
R
— UCCD CCD
W
Reset All zeros
Figure 10-14. Transfer Error Check Disable Register (LTEDR)
Table 10-17. LTEDR Field Descriptions
Bits Name Description
0 BMD Bus monitor disable
0 Bus monitor is enabled.
1 Bus monitor is disabled, but internal bus time-outs can still occur.
1 FCTD FCM command time-out disable
0 FCM command timer is enabled.
1 FCM command time-out is disabled, but internal FCM command timer can terminate command waits.
2 PARD ECC error checking disabled.
0 ECC error checking is enabled.
1 ECC error checking is disabled.
3–4 — Reserved
5 WPD Write protect error checking disable.
0 Write protect error checking is enabled.
1 Write protect error checking is disabled.
6–11 — Reserved
12 CSD Chip select error checking disable.
0 Chip select error checking is enabled.
1 Chip select error checking is disabled.
13–29 — Reserved
30 UCCD UPM Run pattern command completion checking disable.
0 UPM Run pattern command completion checking is enabled.
1 UPM Run pattern command completion checking is disabled.
31 CCD FCM command completion checking disable.
0 Command completion checking is enabled.
1 Command completion checking is disabled.