Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-25
Table 10-16 describes LTESR fields.
Table 10-16. LTESR Field Descriptions
Bits Name Description
0 BM Bus monitor time-out
0 No local bus monitor time-out occurred.
1 Local bus monitor time-out occurred. No data beat was acknowledged on the bus within
LBCR[BMT] x LBCR[BMTPS] bus clock cycles from the start of a transaction.
1 FCT FCM command time-out
0 No FCM command time-out occurred.
1 A CW0, CW1, CW2, or CW3 command issued to FCM timed-out with respect to the timer configured by
FMR[CWTO].
2 PAR ECC error for FCM mode
0 No local bus ECC error
1 Uncorrectable ECC error (FCM). LTEATR[PB] indicates the block that caused the error and LTEATR[BNK]
indicates which memory controller bank was accessed.
3–4 — Reserved
5 WP Write protect error
0 No write protect error occurred.
1 A write was attempted to a local bus memory region that was defined as read-only in the memory
controller. Usually, in this case, a bus monitor time-out will occur (as the cycle is not automatically
terminated).
6–11 — Reserved
12 CS Chip select error
0 No chip select error occurred.
1 A transaction was sent to the eLBC that did not hit any memory bank.
13–29 — Reserved
30 UCC UPM Run pattern (MxMR[OP]=11) command completion event
0 No UPM Run pattern operation in progress, or operation pending.
1 UPM Run pattern operation has completed, allowing software to continue processing of results.
31 CC FCM command completion event
0 No FCM operation in progress, or operation pending.
1 FCM operation has completed, allowing software to continue processing of results.