Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-24 Freescale Semiconductor
Table 10-15 describes LURT fields.
10.3.1.9 Transfer Error Status Register (LTESR)
The transfer error status register (LTESR) indicates the cause of an error or event. LTESR, shown in
Figure 10-13, is a write-1-to-clear register. Reading LTESR occurs normally; however, write operations
can clear but not set bits. A bit is cleared whenever the register is written, and the data in the corresponding
bit location is a 1. For example, to clear only the write protect error bit (LTESR[WP]) without affecting
other LTESR bits, 0x0400_0000 should be written to the register. After any error/event reported by
LTESR, LTEATR[V] must be cleared for LTESR to updated again.
Table 10-15. LURT Field Descriptions
Bits Name Description
0–7 LURT UPM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period according
to the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given MRTPR[PTP] = 32, the
LURT value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required service
period of 15.6 µs.
Note that the reset value (0x00) sets the maximum period to 256 x MRTPR[PTP] system clock cycles.
8–31 — Reserved
Offset 0x0_50B0 Access: w1c
0 1 2 3 4 5 6 11 12 13 15
R
BM FCT PA R — WP — CS —
W
Reset All zeros
16 29 30 31
R
— UCC CC
W
Reset All zeros
Figure 10-13. Transfer Error Status Register (LTESR)
TimerPeriod
LURT
Fsystemclock
MRTPR PTP
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