Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-23
Mode Register (FMR).” Writing LSOR has the same effect as setting a special controller mode and
performing a dummy access to a bank associated with the controller in question, but use of LSOR avoids
changing settings for the address space occupied by the bank. More details of special operation sequences
appear in Section 10.4.4.2.1, “UPM Programming Example (Two Sequential Writes to the RAM Array).”
Table 10-14 describes LSOR.
10.3.1.8 UPM Refresh Timer (LURT)
The UPM refresh timer (LURT), shown in Figure 10-12, generates a refresh request for all valid banks that
selected a UPM machine and are refresh-enabled (MxMR[RFEN] = 1). Each time the timer expires, a
qualified bank generates a refresh request using the selected UPM. The qualified banks rotate their
requests.
Offset 0x0_5090 Access: Read/Write
0 28 29 31
R
— BANK
W
Reset All zeros
Figure 10-11. Special Operation Initiation Register (LSOR)
Table 10-14. LSOR Field Description
Bits Name Description
0–28 — Reserved
29–31 BANK Bank on which a special operation is initiated. If the bank identified by BANK is marked valid (BRn[V] set) and
the bank is controlled by a memory controller whose current mode OP is non-zero—or a special
operation—eLBC will request the special operation to be activated on the selected bank when this field is
written. Otherwise, writing this field has no effect.
000 Bank 0 is triggered for special operation
...
011 Bank 3 is triggered for special operation
100–111Reserved
Offset 0x0_50A0 Access: Read/Write
078 31
R
LURT —
W
Reset All zeros
Figure 10-12. UPM Refresh Timer (LURT)