Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-21
10.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR)
The refresh timer prescaler register (MRTPR), shown in Figure 10-8, is used to divide the system clock to
provide the UPM refresh timers clock.
Table 10-12 describes MRTPR fields.
10.3.1.6 UPM/FCM Data Register (MDR)
The memory data register (MDR), shown in Figure 10-9 and Figure 10-10, contains data written to or read
from the RAM array for UPM read or write commands. MDR also contains data written to or read from
an external NAND Flash EEPROM for FCM write address, write data, and read status commands. MDR
must be set up before issuing a write command to the UPM, or before issuing a FCM operation sequence
that uses MDR to source address or data bytes.
22–25 TLF Refresh loop field. Determines the number of times a loop defined in the UPMn will be executed for a refresh
service pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
26–31 MAD Machine address. RAM address pointer for the command executed. This field is incremented by 1, each time
the UPM is accessed and the OP field is set to WRITE or READ. Address range is 64 words per UPMn.
Offset 0x0_5084 Access: Read/Write
078 31
R
PTP —
W
Reset All zeros
Figure 10-8. Memory Refresh Timer Prescaler Register (MRTPR)
Table 10-12. MRTPR Field Descriptions
Bits Name Description
0–7 PTP Refresh timers prescaler. Determines the period of the refresh timers input clock. The system clock is divided
by PTP except when the value is 00000_0000, which represents the maximum divider of 256.
8–31 — Reserved
Table 10-11. MxMR Field Descriptions (continued)
Bits Name Description