Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-20 Freescale Semiconductor
8–9 DS Disable timer period. Guarantees a minimum time between accesses to the same memory bank controlled
by UPMn. The disable timer is turned on by the TODT bit in the RAM array word, and when expired, the UPMn
allows the machine access to handle a memory pattern to the same bank. Accesses to a different bank by
the same UPMn is also allowed. To avoid conflicts between successive accesses to different banks, the
minimum pattern in the RAM array for a request serviced, should not be shorter than the period established
by DS.
00 1-bus clock cycle disable period
01 2-bus clock cycle disable period
10 3-bus clock cycle disable period
11 4-bus clock cycle disable period
10–12 G0CL General line 0 control. Determines which logical address line can be output to the LGPL0 pin when the UPMn
is selected to control the memory access.
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
13 GPL4 LGPL4 output line disable. Determines how the LGPL4/LUPWAIT pin is controlled by the corresponding bits
in the UPMn array. See Table 10-40 on page 10-75.
14–17 RLF Read loop field. Determines the number of times a loop defined in the UPMn will be executed for a burst- or
single-beat read pattern or when MxMR[OP] = 11 (run command)
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
18–21 WLF Write loop field. Determines the number of times a loop defined in the UPMn will be executed for a burst- or
single-beat write pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Table 10-11. MxMR Field Descriptions (continued)
Bits Name Description
Value LGPL4/LUPWAIT
Pin Function
Interpretation of UPM Word Bits
G4T1/DLT3 G4T3/WAEN
0 LGPL4 (output) G4T1 G4T3
1 LUPWAIT (input) DLT3 WAEN