Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-19
10.3.1.4 UPM Mode Registers (MxMR)
The UPM machine mode registers (MAMR, MBMR and MCMR), shown in Figure 10-7, contain the
configuration for the three UPMs.
Table 10-11 describes UPM mode fields.
Offset MAMR: 0x0_5070
MBMR: 0x0_5074
MCMR: 0x0_5078
Access: Read/Write
0 1 2 3 4 5 7 8 9 10 12 13 14 15
R
— RFEN OP UWPL — DS G0CL GPL4 RLF
W
Reset All zeros
16 17 18 21 22 25 26 31
R
RLF WLF TLF
MAD
W
Reset All zeros
Figure 10-7. UPM Mode Registers (MxMR)
Table 10-11. MxMR Field Descriptions
Bits Name Description
0—Reserved
1 RFEN Refresh enable. Indicates that the UPM needs refresh services. This bit must be set for UPMA (refresh
executor) if refresh services are required on any UPM assigned chip selects. If MAMR[RFEN] = 0, no refresh
services can be provided, even if UPMB and/or UPMC have their RFEN bit set.
0 Refresh services are not required
1 Refresh services are required
2–3 OP Command opcode. Determines the command executed by the UPMn when a memory access hits a UPM
assigned bank.
00 Normal operation
01 Write to UPM array. On the next memory access that hits a UPM assigned bank, write the contents of the
MDR into the RAM location pointed to by MAD. After the access, MAD is automatically incremented.
10 Read from UPM array. On the next memory access that hits a UPM assigned bank, read the contents of
the RAM location pointed to by MAD into the MDR. After the access, MAD is automatically incremented.
11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern written in the
RAM array. The pattern run starts at the location pointed to by MAD and continues until the LAST bit is
set in the RAM word.
4 UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT pin when in UPM mode.
0 LUPWAIT is active high.
1 LUPWAIT is active low.
5–7 —
Reserved