Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-18 Freescale Semiconductor
10.3.1.3 UPM Memory Address Register (MAR)
Figure 10-6 shows the fields of the UPM memory address register (MAR).
Table 10-10 describes the MAR fields.
19 BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
20–22 — Reserved
23 BI Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses.
1 The bank does not support burst accesses. The selected UPM executes burst accesses as a series of
single accesses.
24–28 — Reserved
29 TRLX Timing relaxed. Works in conjunction with EHTR to extend hold time on read accesses.
30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
access from the current bank and the next access.
TRLX EHTR Meaning
0 0 The memory controller generates normal timing. No additional cycles are inserted.
0 1 1 idle clock cycle is inserted.
1 0 4 idle clock cycles are inserted.
1 1 8 idle clock cycles are inserted.
31 — Reserved
Offset 0x0_5068 Access: Read/Write
0 31
R
A
W
Reset All zeros
Figure 10-6. UPM Memory Address Register (MAR)
Table 10-10. MAR Field Descriptions
Bits Name Description
0–31 A Address that can be output to the address signals.
Table 10-9. ORn—UPM Field Descriptions (continued)
Bits Name Description