Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-14 Freescale Semiconductor
10.3.1.2.3 Option Registers (ORn)—FCM Mode
Figure 10-4 shows the bit fields for ORn when the corresponding BRn[MSEL] selects the FCM machine.
29 TRLX Timing relaxed. Modifies the settings of timing parameters for slow memories or peripherals.
0 Normal timing is generated by the GPCM.
1 Relaxed timing on the following parameters:
• Adds an additional cycle between the address and control signals (only if ACS is not equal to 00).
• Doubles the number of wait states specified by SCY, providing up to 30 wait states.
• Works in conjunction with EHTR to extend hold time on read accesses.
•LCS
n (only if ACS is not equal to 00) and LWE signals are negated one cycle earlier during writes.
30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
access from the current bank and the next access.
TRLX EHTR Meaning
0 0 The memory controller generates normal timing. No additional
cycles are inserted.
0 1 1 idle clock cycle is inserted.
1 0 4 idle clock cycles are inserted.
1 1 8 idle clock cycles are inserted.
31 — Reserved.
Offset OR0: 0x0_5004
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
Access: Read/Write
0 15
R
AM
W
Reset All zeros
16 17 18 19 20 21 22 23 24 25 27 28 29 30 31
R
AM — BCTLD — PGS CSCT CST CHT SCY RST
TRLX
EHTR —
W
Reset All zeros
1
Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared.
Figure 10-4. Option Registers (ORn) in FCM Mode
Table 10-7. ORn—GPCM Field Descriptions (continued)
Bits Name Description