Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xxxix
Tables
Table
Number Title
Page
Number
5-43 RTEVR Bit Settings.............................................................................................................. 5-44
5-44 RTALR Bit Settings .............................................................................................................. 5-45
5-45 PIT Signal Properties ............................................................................................................ 5-48
5-46 PIT External Signal—Detailed Signal Descriptions............................................................. 5-48
5-47 PIT Register Address Map....................................................................................................5-49
5-48 PTCNR Bit Settings .............................................................................................................. 5-49
5-49 PTLDR Bit Settings .............................................................................................................. 5-50
5-50 PTPSR Bit Settings ............................................................................................................... 5-51
5-51 PTCTR Bit Settings............................................................................................................... 5-51
5-52 PTEVR Bit Settings .............................................................................................................. 5-52
5-53 GTM Signal Properties.......................................................................................................... 5-56
5-54 GTM External Signals—Detailed Signal Descriptions......................................................... 5-57
5-55 GTM Register Address Map ................................................................................................. 5-58
5-56 GTCFR1 Bit Settings ............................................................................................................ 5-59
5-57 GTCFR2 Bit Settings ............................................................................................................ 5-61
5-58 GTMDR Bit Settings............................................................................................................. 5-62
5-59 GTRFR Bit Settings .............................................................................................................. 5-63
5-60 GTCPRn Bit Settings ............................................................................................................ 5-64
5-61 GTCNR Bit Settings.............................................................................................................. 5-64
5-62 GTEVRn Bit Settings............................................................................................................ 5-65
5-63 GTPSRn Bit Settings............................................................................................................. 5-65
5-64 System Control Signals—Detailed Signal Descriptions....................................................... 5-70
5-65 Power Management Controller Registers Memory Map...................................................... 5-70
5-66 PMCCR Bit Settings ............................................................................................................. 5-71
5-67 Software-Controller Power-Down States—Basic Description ............................................. 5-71
6-1 Arbiter Register Map .............................................................................................................. 6-2
6-2 ACR Field Descriptions.......................................................................................................... 6-3
6-3 ATR Field Descriptions........................................................................................................... 6-5
6-4 AEER Bit Settings .................................................................................................................. 6-5
6-5 AER Field Descriptions .......................................................................................................... 6-6
6-6 AIDR Field Descriptions ........................................................................................................ 6-7
6-7 AMR Field Descriptions ......................................................................................................... 6-8
6-8 AEATR Field Descriptions .....................................................................................................6
-9
6-9 AEADR Field Descriptions .................................................................................................. 6-11
6-10 AERR Field Descriptions...................................................................................................... 6-11
6-11 Address Only Transaction Type Encoding............................................................................ 6-16
6-12 Reserved Transaction Type Encoding................................................................................... 6-17
6-13 Illegal Transaction Type Encoding ....................................................................................... 6-17
7-1 Device Revision Level Cross-Reference .............................................................................. 7-13
7-2 MSR Bit Descriptions ........................................................................................................... 7-18
7-3 e300 HID0 Bit Descriptions.................................................................................................. 7-22