Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-13
20 CSNT Chip select negation time. Determines when LCS
n and LWE are negated during an external memory write
access handled by the GPCM, provided that ACS  00 (when ACS = 00, only LWE
is affected by the setting
of CSNT). This helps meet address/data hold times for slow memories and peripherals.
0LCS
n and LWE are negated normally.
1LCS
n and LWE are negated earlier depending on the value of LCRR[CLKDIV].
LCRR
[CLKDIV]
CSNT Meaning
x0LCS
n and LWE are negated normally.
21LCSn and LWE are negated normally.
4 or 8 1 LCSn and LWE are negated one quarter bus clock cycle earlier.
21–22 ACS Address to chip-select setup. Determines the delay of the LCS
n assertion relative to the address change
when the external memory access is handled by the GPCM. At system reset, OR0[ACS] = 11.
LCRR
[CLKDIV]
Value Meaning
x00LCS
n is output at the same time as the address lines. Note that this
overrides the value of CSNT such that CSNT = 0.
01 Reserved.
210LCS
n is output one half bus clock cycle after the address lines.
11 LCSn is output one half bus clock cycle after the address lines.
4 or 8 10 LCSn is output one quarter bus clock cycle after the address lines.
11 LCSn is output one half bus clock cycle after the address lines.
23 XACS Extra address to chip-select setup. Setting this bit increases the delay of the LCSn assertion relative to the
address change when the external memory access is handled by the GPCM. After a system reset,
OR0[XACS] = 1.
0 Address to chip-select setup is determined by ORx[ACS] and LCRR[CLKDIV].
1 Address to chip-select setup is extended (see Table 10-32 and Ta ble 1 0-3 3).
24–27 SCY Cycle length in bus clocks. Determines the number of wait states inserted in the bus cycle, when the GPCM
handles the external memory access. Thus it is the main parameter for determining cycle length. The total
cycle length depends on other timing attribute settings. After a system reset, OR0[SCY] = 1111.
0000 No wait states
0001 1 bus clock cycle wait state
...
1111 15 bus clock cycle wait states
28 SETA External address termination.
0 Access is terminated internally by the memory controller unless the external device asserts LGTA
earlier
to terminate the access.
1 Access is terminated externally by asserting the LGTA
external pin. (Only LGTA can terminate the access).
Table 10-7. ORn—GPCM Field Descriptions (continued)
Bits Name Description