Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-12 Freescale Semiconductor
10.3.1.2.2 Option Registers (ORn)—GPCM Mode
Figure 10-3 shows the bit fields for ORn when the corresponding BRn[MSEL] selects the GPCM machine.
Table 10-7 describes ORn fields for GPCM mode.
1111_1111_1111_1111_0 64 Kbytes
1111_1111_1111_1111_1 32 Kbytes
Offset OR0: 0x0_5004
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
Access: Read/Write
0 15
R
AM
W
Reset All zeros
16 17 18 19 20 21 22 23 24 27 28 29 30 31
R
AM — BCTLD CSNT ACS XACS SCY SETA
TRLX
EHTR —
W
Reset All zeros
1
Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared.
Figure 10-3. Option Registers (ORn) in GPCM Mode
Table 10-7. ORn—GPCM Field Descriptions
Bits Name Description
0–16 AM GPCM address mask. Masks corresponding BRn bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked and therefore don’t care for address checking.
1 Corresponding address bits are used in the comparison between base and transaction addresses.
17–18 — Reserved
19 BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
Table 10-6. Memory Bank Sizes in Relation to Address Mask (continued)
AM Memory Bank Size