Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-11
The ORn registers are interpreted differently depending on which of the three machine types is selected
for that bank. Because bank 0 can be used to boot, the reset value of OR0 may be different depending on
power-on configuration options. Table 10-5 shows the reset values for OR0.
10.3.1.2.1 Address Mask
The address mask field of the option registers (ORn[AM]) masks up to 17 corresponding BRn[BA] fields.
The 15 LSBs of the 32-bit internal transaction address do not participate in bank address matching in
selecting a bank for access. Masking address bits independently allows external devices of different size
address ranges to be used. Address mask bits can be set or cleared in any order in the field, allowing a
resource to reside in more than one area of the address map. Table 10-6 shows memory bank sizes from
32 Kbytes to 4 Gbytes. Memory block sizes vary from 32 Kbytes to 4 Gbytes in FCM mode, and
32 Kbytes to 64 Mbytes in GPCM and UPM modes.
Table 10-5. Reset value of OR0 Register
Boot Source OR0 Reset Value
FCM (small page NAND Flash) 0000_03AE
FCM (large page NAND Flash) 0000_07AE
GPCM 0000_0FF7
eLBC not used as a boot source 0000_0F07
Table 10-6. Memory Bank Sizes in Relation to Address Mask
AM Memory Bank Size
0000_0000_0000_0000_0 4 Gbytes
1000_0000_0000_0000_0 2 Gbytes
1100_0000_0000_0000_0 1 Gbyte
1110_0000_0000_0000_0 512 Mbytes
1111_0000_0000_0000_0 256 Mbytes
1111_1000_0000_0000_0 128 Mbytes
1111_1100_0000_0000_0 64 Mbytes
1111_1110_0000_0000_0 32 Mbytes
1111_1111_0000_0000_0 16 Mbytes
1111_1111_1000_0000_0 8 Mbytes
1111_1111_1100_0000_0 4 Mbytes
1111_1111_1110_0000_0 2 Mbytes
1111_1111_1111_0000_0 1 Mbyte
1111_1111_1111_1000_0 512 Kbytes
1111_1111_1111_1100_0 256 Kbytes
1111_1111_1111_1110_0 128 Kbytes