Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-10 Freescale Semiconductor
Table 10-4 describes BRn fields.
10.3.1.2 Option Registers (OR0–OR3)
The ORn registers define the sizes of memory banks and access attributes. The ORn attribute bits support
the following three modes of operation as defined by BRn[MSEL]:
• GPCM mode
• FCM mode
• UPM mode
Table 10-4. BRn Field Descriptions
Bits Name Description
0–16 BA Base address. The upper 17 bits of each base register are compared to the address on the address bus to
determine if the bus master is accessing a memory bank controlled by the memory controller. Used with the
address mask bits ORn[AM].
17–18 — Reserved
19–20 PS Port size. Specifies the port size of this memory region. For BR0, PS is configured from the field in reset
configuration word as loaded during reset. For all other banks the value is reset to 00 (port size not defined).
00 Reserved
01 8-bit (supported for GPCM, UPM, FCM)
10 16-bit (supported for GPCM, UPM)
11 Reserved
21–22 DECC Specifies the method for data error checking.
00 Data error checking disabled. No ECC generation for FCM.
01 ECC checking is enabled, but ECC generation is disabled, for FCM on full-page transfers.
10 ECC checking and generation are enabled for FCM on full-page transfers.
11 Reserved
23 WP Write protect.
0 Read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert LCS
n on write cycles to this
memory bank. LTESR[WP] is set (if WP is set) if a write to this memory bank is attempted, and a local bus
error interrupt is generated (if enabled), terminating the cycle.
24–26 MSEL Machine select. Specifies the machine to use for handling memory operations.
000 GPCM (possible reset value)
001 FCM (possible reset value)
010 Reserved
011 Reserved
100 UPMA
101 UPMB
110 UPMC
111 Reserved
27–30 — Reserved
31 V Valid bit. Indicates that the contents of the BRn and ORn pair are valid. LCS
n does not assert unless V is set
(an access to a region that has no valid bit set may cause a bus time-out). After a system reset, only BR0[V]
is set.
0 This bank is invalid.
1 This bank is valid.