Information
Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-9
10.3.1 Register Descriptions
This section provides a detailed description of the eLBC configuration, status, and control registers with
detailed bit and field descriptions.
Address offsets in the eLBC address range that are not defined in Table 10-3 should not be accessed for
reading or writing. Similarly, only zero should be written to reserved bits of defined registers, as writing
ones can have unpredictable results in some cases.
Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to them has
no effect.
10.3.1.1 Base Registers (BR0–BR3)
The base registers (BRn), shown in Figure 10-2, contain the base address and address types for each
memory bank. The memory controller uses this information to compare the address bus value with the
current address accessed. Each register (bank) includes a memory attribute and selects the machine for
memory operation handling. Note that after system reset, BR0[V] is set, BR1[V]–BR3[V] are cleared, and
the value of BR0[PS] reflects the initial port size configured by the boot ROM location field of the reset
configuration word.
0x100 FECC0—Flash ECC block 0 register R 0x0000_0000 10.3.1.23/10-38
0x104 FECC1—Flash ECC block 1 register R 0x0000_0000 10.3.1.23/10-38
0x108 FECC2—Flash ECC block 2 register R 0x0000_0000 10.3.1.23/10-38
0x10C FECC3—Flash ECC block 3 register R 0x0000_0000 10.3.1.23/10-38
Offset BR0: 0x0_5000
BR1: 0x0_5008
BR2: 0x0_5010
BR3: 0x0_5018
Access: Read/Write
0 16171819202122 23 24 2627 3031
R
BA — PS DECC WP MSEL — V
W
Reset0000000000000000000PS00 0 00M0000V
1
1
BR0 has its valid bit (V) set for RCWH[ROMLOC] = LBC. Thus bank 0 is valid with the port size (PS) configured from
RCWH[ROMLOC] as loaded during reset. M = 0 for MSEL of GPCM, 1 for MSEL of FCM at boot. All other base registers have
all bits cleared to zero during reset.
Figure 10-2. Base Registers (BRn)
Table 10-3. Enhanced Local Bus Controller Registers (continued)
Enhanced Local Bus Controller—Block Base Address 0x0_5000
Offset Register Access Reset Section/Page