Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-8 Freescale Semiconductor
0x070 MAMR—UPMA mode register R/W 0x0000_0000 10.3.1.4/10-19
0x074 MBMR—UPMB mode register R/W 0x0000_0000 10.3.1.4/10-19
0x078 MCMR—UPMC mode register R/W 0x0000_0000 10.3.1.4/10-19
0x07C–
0x080
Reserved — — —
0x084 MRTPR—Memory refresh timer prescaler register R/W 0x0000_0000 10.3.1.5/10-21
0x088 MDR—UPM/FCM data register R/W 0x0000_0000 10.3.1.6/10-21
0x08C Reserved — — —
0x090 LSOR—Special operation initiation register R/W 0x0000_0000 10.3.1.7/10-22
0x094–
0x09C
Reserved — — —
0x0A0 LURT—UPM refresh timer R/W 0x0000_0000 10.3.1.4/10-19
0x0A4–
0x0AC
Reserved — — —
0x0B0 LTESR—Transfer error status register w1c 0x0000_0000 10.3.1.9/10-24
0x0B4 LTEDR—Transfer error disable register R/W 0x0000_0000 10.3.1.10/10-26
0x0B8 LTEIR—Transfer error interrupt register R/W 0x0000_0000 10.3.1.11/10-27
0x0BC LTEATR—Transfer error attributes register R/W 0x0000_0000 10.3.1.12/10-28
0x0C0 LTEAR—Transfer error address register R/W 0x0000_0000 10.3.1.13/10-29
0x0C4 LTECCR—Transfer error ECC register w1c 0x0000_0000 10.3.1.14/10-29
0x0C8–
0x0CC
Reserved — — —
0x0D0 LBCR—Configuration register R/W 0x0004_0000 10.3.1.15/10-30
0x0D4 LCRR—Clock ratio register R/W 0x8000_0008 10.3.1.16/10-31
0x0D8–
0x0DC
Reserved — — —
0x0E0 FMR—Flash mode register R/W 0x0000_0n00 10.3.1.17/10-32
0x0E4 FIR—Flash instruction register R/W 0x0000_0000 10.3.1.18/10-34
0x0E8 FCR—Flash command register R/W 0x0000_0000 10.3.1.19/10-35
0x0EC FBAR—Flash block address register R/W 0x0000_0000 10.3.1.20/10-36
0x0F0 FPAR—Flash page address register R/W 0x0000_0000 10.3.1.21/10-36
0x0F4 FBCR—Flash byte count register R/W 0x0000_0000 10.3.1.22/10-38
0x0F8–
0x0FC
Reserved — — —
Table 10-3. Enhanced Local Bus Controller Registers (continued)
Enhanced Local Bus Controller—Block Base Address 0x0_5000
Offset Register Access Reset Section/Page