Information
Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-7
10.3 Memory Map/Register Definition
Table 10-3 shows the memory mapped registers of the eLBC. Undefined 4-byte address spaces within
offset 0x000–0xFFF are reserved.
LDVAL O Local bus data valid (eLBC debug mode only)
State
Meaning
Asserted/Negated—For a read, LDVAL asserts for one bus cycle in the cycle immediately
preceding the sampling of read data on LD. For a write, LDVAL asserts for one bus
cycle during the final cycle for which the current write data on LD is valid. During
burst transfers, LDVAL asserts for each data beat.
Timing Assertion/Negation—Valid only while the eLBC is in system debug mode. In debug mode,
LDVAL asserts when the eLBC generates a data transfer acknowledge.
LSRCID[0:4] O Local bus source ID (eLBC debug mode only). In debug mode, all LSRCID[0:4] pins are driven high
unless LSRCID[0:4] is driving a debug source ID for identifying the internal system device controlling
the eLBC.
State
Meaning
Asserted/Negated—Is valid for one cycle prior to the assertion of LCS
.
LBC_PM_REF_10 O Status of uncorrectable ECC error in FCM during boot loading from Flash
State
Meaning
Asserted/Negated—LBC_PM_REF_10 is asserted in case FCM gets an uncorrectable
ECC error, when ECC checking is enabled. The signal would remain asserted until
next NAND operation.
Table 10-3. Enhanced Local Bus Controller Registers
Enhanced Local Bus Controller—Block Base Address 0x0_5000
Offset Register Access Reset Section/Page
0x000 BR0—Base register 0 R/W 0x0000_nnnn 10.3.1.1/10-9
0x008 BR1—Base register 1 R/W 0x0000_0000 10.3.1.1/10-9
0x010 BR2—Base register 2 R/W 0x0000_0000 10.3.1.1/10-9
0x018 BR3—Base register 3 R/W 0x0000_0000 10.3.1.1/10-9
0x020–0x038 Reserved — — —
0x004 OR0—Options register 0 R/W 0x0000_0FF7 10.3.1.2/10-10
0x00C OR1—Options register 1 R/W 0x0000_0000 10.3.1.2/10-10
0x014 OR2—Options register 2 R/W 0x0000_0000 10.3.1.2/10-10
0x01C OR3—Options register 3 R/W 0x0000_0000 10.3.1.2/10-10
0x024–
0x064
Reserved — — —
0x068 MAR—UPM address register R/W 0x0000_0000 10.3.1.3/10-18
0x06C Reserved — — —
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued)
Signal I/O Description