Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-6 Freescale Semiconductor
LOE
/LGPL2/
LFRE
O GPCM output enable/General-purpose line 2/FCM read enable.
State
Meaning
Asserted/Negated—Controls the output buffer of memory when accessing
memory/devices in GPCM mode.
In UPM mode, LGPL2 is one of six general purpose signals; it is driven with a value
programmed into the UPM array.
LFRE
enables data read cycles from NAND Flash EEPROMs controlled by FCM.
LGPL3/
LFWP
O General-purpose line 3/FCM write protect.
State
Meaning
Asserted/Negated—In UPM mode, LGPL3 is one of six general purpose signals; it is
driven with a value programmed into the UPM array.
In FCM mode LFWP
protects NAND Flash EEPROMs from accidental erasure and
programming when LFWP is asserted low—see Section 10.3.1.17, “Flash Mode
Register (FMR),” for programming of FCM operations to control LFWP.
LGTA/LGPL4/
LFRB
/
LUPWAIT
I/O GPCM transfer acknowledge/General-purpose line 4/FCM Flash ready-busy/UPM wait.
State
Meaning
Asserted/Negated—Input in GPCM or FCM modes used for transaction termination. It
may also be configured as one of six general-purpose output signals when in UPM
mode or as an input to force the UPM controller to wait for the memory/device. FCM
uses LFRB to stall during long-latency read and programming operations,
continuing once LFRB
returns high.
LGPL5 O General-purpose line 5
State
Meaning
Asserted/Negated—One of six general purpose signals when in UPM mode, and drives
a value programmed in the UPM array.
LBCTL O Data buffer control. The memory controller activates LBCTL for the local bus when a GPCM-, UPM-,
or FCM-controlled bank is accessed. Buffer control is disabled by setting ORn[BCTLD].
State
Meaning
Asserted/Negated—The LBCTL pin normally functions as a write/read
control for a bus
transceiver connected to the LD lines. Note that an external data buffer must not
drive the LD lines in conflict with the eLBC when LBCTL is high, because LBCTL
remains high after reset and during address phases.
LA[0:25] O Nonmultiplexed address bus. All bits driven on LA[0:25] are defined for 8-bit port sizes. For 16-bit port
sizes LA[25] is a don’t care.
State
Meaning
Asserted/Negated—LA is the address bus used to transmit addresses to external RAM
devices. Refer to Section 10.5, “Initialization/Application Information,” for address
signal multiplexing.
LD[0:15] I/O Data bus. For a port size of 16 bits, LD[0:7] connect to the most-significant byte lane (at address offset
0), while LD[8:15] connect to the least-significant byte lane (at address offset 1). For a port size of 8
bits, only LD[0:7] are connected to the external RAM.
State
Meaning
Asserted/Negated—LD is the 16-bit data bus through which external RAM devices
transfer data.
LCLK0 O Local bus clocks
State
Meaning
Asserted/Negated—LCLK0 drive an identical bus clock signal for distributed loads.
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued)
Signal I/O Description