Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-5
Table 10-2 shows the detailed external signal descriptions for the eLBC.
LBCTL — — Data buffer control 1 O
LA[0:25] — — Non-multiplexed address bus 26 O
LD[0:15] — — Data bus 16 I/O
LCLK0 — — Local bus clocks 1 O Driven
LDVAL — eLBC debug Local bus data valid 1 O
LSRCID[0:4] — eLBC debug Local bus source ID 5 O
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions
Signal I/O Description
LCS
[0:3] O Chip selects. Four chip selects are provided that are mutually exclusive.
State
Meaning
Asserted/Negated—Used to enable specific memory devices or peripherals connected to
the eLBC. LCS[0:3] are provided on a per-bank basis with LCS0 corresponding to
the chip select for memory bank 0, which has the memory type and attributes
defined by BR0 and OR0.
LWE0
/
LFWE0/
LBS0,
LWE1/
LBS1
O GPCM write enable 0/FCM write enable/UPM byte select 0. These signals select or validate each
byte lane of the data bus. For an 8-bit port size, bit 0 is the only defined signal. The least-significant
address bits of each access also determine which byte lanes are considered valid for a given data
transfer.
State
Meaning
Asserted/Negated—For GPCM operation, LWE[0:1] assert for each byte lane enabled for
writing.
LFWE0 enables command, address, and data writes to NAND Flash EEPROMs
controlled by FCM.
LBS
[0:1] are programmable byte-select signals in UPM mode. See
Section 10.4.4.4, “RAM Array,” for programming details about LBS[0:1].
Timing Assertion/Negation—See Section 10.4.2, “General-Purpose Chip-Select Machine
(GPCM),” for details regarding the timing of LWE
[0:1].
LGPL0/
LFCLE
O General purpose line 0/FCM command latch enable.
State
Meaning
Asserted/Negated—In UPM mode, LGPL0 is one of six general purpose signals; it is
driven with a value programmed into the UPM array.
In FCM mode, LFCLE enables command cycles to NAND Flash EEPROMs.
LGPL1/
LFALE
O General-purpose line 1/FCM address latch enable.
State
Meaning
Asserted/Negated—In UPM mode, LGPL1 is one of six general purpose signals; it is
driven with a value programmed into the UPM array.
In FCM mode, LFALE enables address cycles to NAND Flash EPROMs.
Table 10-1. Signal Properties—Summary (continued)
Name
Alternate
Function(s)
Mode Descriptions
No. of
Signals
I/O
Reset State
(Outputs)