Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 473 (19x19) MPC83xx 32-Bit Single-Core 333 MHz

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

xxxviii Freescale Semiconductor

Tables

Table

Number Title

Page

Number

5-2 Local Access Windows Example............................................................................................ 5-2

5-3 Format of Window Definitions ............................................................................................... 5-3

5-4 Local Access Register Memory Map...................................................................................... 5-4

5-5 IMMRBAR Bit Settings.......................................................................................................... 5-6

5-6 ALTCBAR Bit Settings........................................................................................................... 5-7

5-7 LBLAWBAR0–LBLAWBAR3 Bit Settings........................................................................... 5-8

5-8 LBLAWBAR0[BASE_ADDR] Reset Value .......................................................................... 5-8

5-9 LBLAWAR0–LBLAWAR3 Bit Settings................................................................................. 5-8

5-10 LBLAWAR0[EN] Reset Value................................................................................................ 5-9

5-11 PCIEXP1LAWBAR Bit Settings.......................................................................................... 5-10

5-12 PCIEXP1LAWAR Bit Settings ............................................................................................. 5-10

5-13 DDRLAWBAR0–DDRLAWBAR1 Bit Settings.................................................................. 5-11

5-14 DDRLAWBAR0[BASE_ADDR] Reset Value..................................................................... 5-11

5-15 DDRLAWAR0–DDRLAWAR1 Bit Settings ........................................................................ 5-12

5-16 DDRLAWAR0[EN] Reset Value .......................................................................................... 5-13

5-17 Overlapping Local Access Windows.................................................................................... 5-13

5-18 System Configuration Register Memory Map...................................................................... 5-15

5-19 SGPRL Bit Settings .............................................................................................................. 5-16

5-20 SGPRH Bit Settings.............................................................................................................. 5-16

5-21 SPRIDR Bit Settings............................................................................................................. 5-17

5-22 PARTID Coding ................................................................................................................... 5-17

5-23 REVID Coding ..................................................................................................................... 5-17

5-24 SPCR Bit Settings ................................................................................................................. 5-18

5-25 SICRL Bit Settings ............................................................................................................... 5-20

5-26 SICRH Bit Settings ............................................................................................................... 5-22

5-27 SICRH[27–31] Bit Settings .................................................................................................. 5-25

5-28 DDRCDR Field Descriptions................................................................................................ 5-27

5-29 DDRDSR Field Descriptions................................................................................................ 5-28

5-30 PECR Field Description........................................................................................................ 5-29

5-31 SDHCCR Field Description.................................................................................................. 5-31

5-32 RTCCR Field Description.....................................................................................................5-32

5-33 WDT Register Address Map................................................................................................. 5-34

5-34 SWCRR Bit Settings............................................................................................................. 5-35

5-35 SWCNR Bit Settings............................................................................................................. 5-36

5-36 SWSRR Bit Settings ............................................................................................................. 5-36

5-37 RTC External Signals............................................................................................................ 5-41

5-38 RTC Register Address Map .................................................................................................. 5-41

5-39 RTCNR Bit Settings.............................................................................................................. 5-42

5-40 RTLDR Bit Settings.............................................................................................................. 5-43

5-41 RTPSR Bit Settings............................................................................................................... 5-43

5-42 RTCTR Bit Settings .............................................................................................................. 5-44