Information
Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-2 Freescale Semiconductor
10.1.1 Overview
The main component of the eLBC is its memory controller, which provides a seamless interface to many
types of memory devices and peripherals. The memory controller is responsible for controlling four
memory banks shared by a GPCM, an FCM, and up to three UPMs. As such, it supports a minimal glue
logic interface to SRAM, EPROM, NOR Flash EEPROM, NAND Flash EEPROM, burstable RAM,
regular DRAM devices, extended data output DRAM devices, and other peripherals. The eLBC also
includes a number of data checking and protection features such as write protection and a bus monitor to
ensure that each bus cycle is terminated within a user-specified period.
10.1.2 Features
The eLBC main features are as follows:
• Memory controller with four memory banks
— 32-bit address decoding with mask
— Variable memory block sizes (32 Kbytes to 4 Gbytes in FCM mode, 32 Kbytes to 64 Mbytes
in GPCM and UPM modes)
— Selection of control signal generation on a per-bank basis
— Data buffer controls activated on a per-bank basis
— Automatic segmentation of large transactions into memory accesses optimized for bus width
and addressing capability
— Write-protection capability
• General-purpose chip-select machine (GPCM)
— Compatible with SRAM, EPROM, NOR Flash EEPROM, and peripherals
— Global (boot) chip-select available at system reset
— Boot chip-select support for 8- and 16-bit devices
— Minimum three-clock access to external devices
— Two byte-write-enable signals (LWE[0:1])
— Output enable signal (LOE)
— External access termination signal (LGTA
)
• NAND Flash control machine (FCM)
— Compatible with small (512+16 bytes) and large (2048+64 bytes) page parallel NAND Flash
EEPROM
— Global (boot) chip-select available at system reset, with 4-Kbyte boot block buffer for
execute-in-place boot loading
— Read-only ECC registers to verify after write operation
— Boot chip-select support for 8-bit devices
— Dual 2-Kbyte/eight 512-byte buffers allow simultaneous data transfer during flash reads and
programming
— Interrupt-driven block transfer for reads and writes