Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-62 Freescale Semiconductor
9.6.1 DDR SDRAM Initialization Sequence
After configuration of all parameters is complete, system software must set
DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 200 s must elapse after
DRAM clocks are stable (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set and any chip select is
enabled) before MEM_EN can be set, so a delay loop in the initialization code may be necessary if
software is enabling the memory controller. If DDR_SDRAM_CFG[BI] is not set, the DDR memory
controller conducts an automatic initialization sequence to the memory, which follows the memory
specifications. If the bypass initialization mode is used, then software can initialize the memory through
the DDR_SDRAM_MD_CNTL register.