Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-60 Freescale Semiconductor
9.5.12 Error Management
The DDR memory controller detects four different kinds of errors: training, single-bit, multi-bit, and
memory select errors. The following discussion assumes all the relevant error detection, correction, and
reporting functions are enabled as described in Section 9.4.1.26, “Memory Error Interrupt Enable
(ERR_INT_EN),” Section 9.4.1.25, “Memory Error Dis able (ERR_DISABLE),” and Section 9.4.1.24,
“Memory Error Detect (ERR_DETECT).”
Multi-bit errors can generate an MCP while single-bit errors generate a normal interrupt to the e300 core.
Single-bit errors are counted and reported based on the ERR_SBE value. When a single-bit error is
detected, the DDR memory controller does the following:
• Corrects the data
• Increments the single-bit error counter ERR_SBE[SBEC]
• Generates a critical interrupt if the counter value ERR_SBE[SBEC] equals the programmable
threshold ERR_SBE[SBET]
• Completes the transaction normally
If a multi-bit error is detected for a read, the DDR memory controller logs the error and generates the
interrupt (if enabled, as described in Section 9.4.1.25, “Memory Error Dis able (ERR_DISABLE)”).
Another error the DDR memory controller detects is a memory select error, which causes the DDR
memory controller to log the error and generate a critical interrupt (if enabled, as described in
Section 9.4.1.24, “Memory Error Detect (ERR_DETECT)”). This error is detected if the address from the
memory request does not fall into any of the enabled, programmed chip select address ranges.
Table 9-47 shows the errors with their descriptions. The final error the memory controller detects is the
automatic calibration error. This error is set if the memory controller detects an error during its training
sequence.
9.6 Initialization/Application Information
System software must configure the DDR memory controller, using a memory polling algorithm at system
start-up, to correctly map the size of each bank in memory. Then, the DDR memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank depths.
System software must also configure the DDR memory controller at system start-up to appropriately
multiplex the row and column address bits for each bank. Refer to row-address configuration in
Section 9.4.1.2, “Chip Select Configuration (CSn_CONFIG).” Address multiplexing occurs according to
these configuration bits.
Table 9-47. Memory Controller Errors
Error Descriptions Action Detect Register
Single-bit ECC
threshold
The number of ECC errors has reached the
threshold specified in the ERR_SBE.
The error is reported
through interrupt if
enabled.
The error control
register only logs
read versus write
Multi-bit ECC
error
A multi-bit ECC error is detected during a read, or
read-modify-write memory operation.
Memory select
error
Read, or write, address does not fall within the
address range of any of the memory banks.