Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-56 Freescale Semiconductor
9.5.8.2.1 Self-Refresh in Sleep Mode
The entry and exit timing for self-refreshing SDRAMs is shown in Figure 9-43 and Figure 9-44.
Figure 9-43. DDR SDRAM Self-Refresh Entry Timing
Figure 9-44. DDR SDRAM Self-Refresh Exit Timing
9.5.9 DDR Data Beat Ordering
Transfers to and from memory are always performed in four-beat bursts (four beats = 16 bytes when a
32-bit bus is used). For transfer sizes other than four beats, the data transfers are still operated as four-beat
bursts. If ECC is enabled and either the access is not doubleword aligned or the size is not a multiple of a
SDRAM Clock
MCS
MCAS
MAn
MDQn
MWE
MRAS
MDQS
(High Impedance)
MCKE
01 2345 67 89101112
SDRAM Clock
MCS
MCAS
MAn
MDQn
MWE
MRAS
MDQS
01 2345 67 202203204205206
MCKE
(High Impedance)
200 Cycles