Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xxxvii
Tables
Table
Number Title
Page
Number
Tabl es
1 Acronyms and Abbreviated Terms........................................................................................... lxi
2-1 MPC8308 Signal Reference by Functional Block.................................................................. 2-3
2-2 Output Signal States During System Reset........................................................................... 2-13
3-1 IMMR Memory Map ..............................................................................................................3-2
4-1 System Control Signals........................................................................................................... 4-1
4-2 External Clock Signals............................................................................................................ 4-2
4-3 Reset Causes ........................................................................................................................... 4-3
4-4 Reset Actions .......................................................................................................................... 4-4
4-5 Reset Configuration Words Source......................................................................................... 4-8
4-6 Selecting Reset Configuration Input Signals .......................................................................... 4-9
4-7 RCWLR Bit Settings............................................................................................................. 4-10
4-8 System PLL VCO Division................................................................................................... 4-11
4-9 System PLL Ratio ................................................................................................................. 4-11
4-10 Reset Configuration Word High Bit Settings........................................................................ 4-12
4-11 Boot Memory Space.............................................................................................................. 4-13
4-12 Boot Sequencer Configuration.............................................................................................. 4-14
4-13 Boot ROM Location.............................................................................................................. 4-15
4-14 eTSEC1 Mode Configuration ............................................................................................... 4-15
4-15 eTSEC2 Mode Configuration ............................................................................................... 4-16
4-16 e300 Core True Little-Endian ............................................................................................... 4-16
4-17 Local Bus Configuration EEPROM Addresses .................................................................... 4-17
4-18 Local Bus Reset Configuration Words Data Structure.......................................................... 4-17
4-19 Local Bus Controller Setting When Loading RCW.............................................................. 4-18
4-20 RCW Values Corresponding to Hard Coded Options........................................................... 4-21
4-21 Hard Coded Reset Configuration Word Low Fields Values ................................................. 4-21
4-22 Hard-Coded Reset Configuration Word High Field Values.................................................. 4-22
4-23 Configurable Clock Units ..................................................................................................... 4-24
4-24 Reset Configuration and Status Registers Memory Map...................................................... 4-25
4-25 Reset Status Register Field Descriptions .............................................................................. 4-26
4-26 RMR Field Descriptions ....................................................................................................... 4-27
4-27 RPR Bit Descriptions............................................................................................................ 4-28
4-28 RCR Bit Settings................................................................................................................... 4-29
4-29 RCER Bit Settings ................................................................................................................ 4-29
4-30 Clock Configuration Registers Memory Map....................................................................... 4-29
4-31 System PLL Mode Register Bit Settings .............................................................................. 4-30
4-32 OCCR Bit Settings................................................................................................................ 4-31
4-33 SCCR Bit Descriptions ......................................................................................................... 4-32
5-1 Local Access Windows Target Interface................................................................................. 5-1