Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-52 Freescale Semiconductor
Figure 9-39 shows the registered DDR SDRAM DIMM single-beat write timing.
Figure 9-39. Registered DDR SDRAM DIMM Burst Write Timing
9.5.7 DDR SDRAM Write Timing Adjustments
The DDR memory controller facilitates system design flexibility by providing a write timing adjustment
parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and DQS. The DDR
SDRAM specification requires DQS be received no sooner than 75% of an SDRAM clock period—and
no later than 125% of a clock period—from the capturing clock edge of the command/address at the
SDRAM. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and
data from the first clock edge occurring one SDRAM clock cycle after the command is launched. The
delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0.
ROW COL
SDRAM Clock
MCS
MCAS
MAn
MDQn
MWE
MRAS
MDQS
COL
D1 D2 D3 D1 D2D0 D3D0
01 2345 67 89101112
ACTTORW
00
MDM[0:3]