Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-51
9.5.5 DDR SDRAM Mode-Set Command Timing
The DDR memory controller transfers the mode register set commands to the SDRAM array, and it uses
the setting of TIMING_CFG_0[MRS_CYC] for the Mode Register Set cycle time.
Figure 9-38 shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE
code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles.
Figure 9-38. DDR SDRAM Mode-Set Command Timing
9.5.6 DDR SDRAM Registered DIMM Mode
To reduce loading, registered DIMMs latch the DDR SDRAM control signals internally before using them
to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay on the DIMMs’
control bus by delaying the data and data mask writes (on SDRAM buses) by an extra SDRAM clock
cycle.
SDRAM Clock
MCS
MCAS
MAn
MDQn
MWE
MRAS
MDQS
MBAn
01 2345 67 89101112
0x4 0x0
Code Code