Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-50 Freescale Semiconductor
Figure 9-36. DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3
9.5.4.1 Clock Distribution
The following list discusses recommendations for clock distribution.
• If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be
used. These buffers were designed for DDR applications.
• PCB traces for DDR clock signals should be short, all on the same layer, and of equal length and
loading.
DDR SDRAM manufacturers provide detailed information on PCB layout and termination issues.
Figure 9-37. DDR SDRAM Clock Distribution Example for 8 DDR SDRAMs
ROW COL
SDRAM Clock
MCS0
MCAS
MAn
MDQ[0:63]
MWE
MRAS
MDQS
MDM[0:7]
00
COL
MCS1
ROW
COL COL
D1 D2 D3 D1 D2D0 D3D0 D1 D2 D3 D1 D2D0 DD0
01 2345 67 89101112
ACTTORW
MCK[2], MCK[2]
MCK[0], MCK[0]
DQ[0:7], DQS[0], DM[0]
DQ[8:15], DQS[1], DM[1]
DQ[16:23], DQS[2], DM[2]
DQ[24:31], DQS[3], DM[3]
ECC[0:7], DQS[8], DM[8]
DDR
CS[0]
A[13:0], BA[2:0], MRAS, MCAS, MWE, CKE
CS[1]
MCK[1], MCK[1]
MCK[2], MCK[2]