Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-49
set to 1/2 DRAM cycle, an additive latency of 0 DRAM cycles is used, and the write latency is 1 DRAM
cycle.
Figure 9-34. DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2
Figure 9-35. DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR
ACTTORW
ROW COL
SDRAM Clock
MCS
MCAS
MAn
MDQn
MWE
MRAS
MDQS
COL
D1 D2 D3 D1 D2D0 D3D0
01 2345 67 89101112
CASLAT
ACTTORW
ROW COL
SDRAM Clock
MCS
MCAS
MAn
MDQn
MWE
MRAS
MDQS
D0 D1 D2 D3
00
MDM[0:7]
WRREC
A10=0
PRECHARGE
PRETOACT
ROW
01 2345 67 89101112
FFFF FF00 FFFF FF