Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-46 Freescale Semiconductor
Latches column address and transfers data from the selected sense amplifier to the output buffer as
determined by the column address. During each succeeding clock edge, additional data is driven
without additional read commands. The amount of data transferred is determined by the burst size
which defaults to 4.
•Write
Latches column address and transfers data from the data pins to the selected sense amplifier as
determined by the column address. During each succeeding clock edge, additional data is
transferred to the sense amplifiers from the data pins without additional write commands. The
amount of data transferred is determined by the data masks and the burst size, which is set to four
by the DDR memory controller.
• Refresh (similar to MCAS before MRAS)
Causes a row to be read in all logical banks (JEDEC SDRAM) as determined by the refresh row
address counter. This refresh row address counter is internal to the SDRAM. After being read, the
row is automatically rewritten in the memory array. All logical banks must be in a precharged state
before executing a refresh. The memory controller also supports posted refreshes, where several
refreshes may be executed at once, and the refresh interval may be extended.
• Mode register set (for configuration)
Allows setting of DDR SDRAM options. These options are: MCAS latency, additive latency, write
recovery, burst type, and burst length. MCAS latency may be chosen as provided by the preferred
SDRAM (some SDRAMs provide MCAS latency {1,2,3}, some provide MCAS latency
{1,2,3,4,5}, and so on). Burst type is always sequential. Although some SDRAMs provide burst
lengths of 1, 2, 4, 8, and page size, this memory controller supports a burst length of 4. For DDR2
in 32-bit bus mode, all 32-byte burst accesses from the platform are split into two 16-byte (that is,
4-beat) accesses to the SDRAMs in the memory controller. The mode register set command is
performed by the DDR memory controller during system initialization. Parameters such as mode
register data, MCAS latency, burst length, and burst type, are set by software in
DDR_SDRAM_MODE[SDMODE] and transferred to the SDRAM array by the DDR memory
controller after DDR_SDRAM_CFG[MEM_EN] is set. If DDR_SDRAM_CFG[BI] is set to
bypass the automatic initialization, then the MODE registers can be configured through software
through use of the DDR_SDRAM_MD_CNTL register.
• Self refresh (for long periods of standby)
Used when the device is in standby for very long periods of time. Automatically generates internal
refresh cycles to keep the data in all memory banks refreshed. Before execution of this command,
the DDR controller places all logical banks in a precharged state.
Table 9-41. DDR SDRAM Command Table
Operation
CKE
Prev.
CKE
Current
MCS MRAS MCAS MWE MBA MA10 MA
Activate H H L L H H Logical bank select Row Row
Precharge select
logical bank
H H L L H L Logical bank select L X
Precharge all logical
banks
HHLLHL X H X