Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xxxvi Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
18-10 Modem Control Register (UMCR1 and UMCR2).............................................................. 18-12
18-11 Line Status Register (ULSR1 and ULSR2) ........................................................................ 18-13
18-12 Scratch Register (USCR) .................................................................................................... 18-14
18-13 Alternate Function Register (UAFR).................................................................................. 18-14
18-14 DMA Status Register (UDSR)............................................................................................ 18-15
18-15 UART Bus Interface Transaction Protocol Example.......................................................... 18-17
19-1 SPI Block Diagram ............................................................................................................... 19-1
19-2 Single-Master/Multi-Slave Configuration ............................................................................ 19-3
19-3 Multiple-Master Configuration............................................................................................. 19-5
19-4 SPMODE-SPI Mode Register Definition ............................................................................. 19-8
19-5 SPI Transfer Format with SPMODE[CP] = 0..................................................................... 19-10
19-6 SPI Transfer Format with SPMODE[CP] = 1..................................................................... 19-10
19-7 SPIE—SPI Event Register Definition................................................................................. 19-11
19-8 SPIM—SPI Mask Register Definition................................................................................ 19-12
19-9 SPI Command Register Definition ..................................................................................... 19-13
19-10 SPI Transmit Data Hold Register Definition ...................................................................... 19-13
19-11 SPI Receive Data Hold Register Definition........................................................................ 19-14
19-12 Example SPMODE[REV] = 0 SPMODE[LEN] = 7 LSB Sent First.................................. 19-14
19-13 Example SPMODE[REV] = 1 SPMODE[LEN] = 7 MSB Sent First................................. 19-14
19-14 Example SPMODE[REV] = 1 SPMODE[LEN] = 15 MSB Sent First............................... 19-14
19-15 Example SPMODE[REV] = 0 SPMODE[LEN] = 15 LSB Sent First................................ 19-15
20-1 JTAG Interface Block Diagram ............................................................................................ 20-1
21-1 GPIO Module Block Diagram .............................................................................................. 21-1
21-2 GPIO Direction Register (GPDIR) ....................................................................................... 21-3
21-3 GPIO Open Drain Register (GPODR).................................................................................. 21-3
21-4 GPIO Data Register (GPDAT).............................................................................................. 21-4
21-5 GPIO Interrupt Event Register (GPIER) .............................................................................. 21-4
21-6 GPIO Interrupt Mask Register (GPIMR).............................................................................. 21-5
21-7 GPIO Interrupt Control Register (GPICR) ........................................................................... 21-5