Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-45
Table 9-40 illustrates examples of address decode when interleaving between two chip selects.
9.5.3 JEDEC Standard DDR SDRAM Interface Commands
The following section describes the commands and timings the controller uses when operating in DDR2
mode.
All read or write accesses to DDR SDRAM are performed by the DDR memory controller using JEDEC
standard DDR SDRAM interface commands. The SDRAM device samples command and address inputs
on rising edges of the memory clock; data is sampled using both the rising and falling edges of DQS. Data
read from the DDR SDRAM is also sampled on both edges of DQS.
The following DDR SDRAM interface commands (summarized in Table 9-41) are provided by the DDR
controller. All actions for these commands are described from the perspective of the SDRAM device.
• Row activate
Latches row address and initiates memory read of that row. Row data is latched in SDRAM sense
amplifiers and must be restored by a precharge command before another row activate occurs.
• Precharge
Restores data from the sense amplifiers to the appropriate row. Also initializes the sense amplifiers
in preparation for reading another row in the memory array (performing another activate
command). Precharge must occur after read or write, if the row address changes on the next open
page mode access.
• Read
Table 9-40. Example of Address Multiplexing for 32-Bit Data Bus Interleaving between
Two Banks with Partial Array Self Refresh Disabled
Row

Col
msb Address from Core Master lsb
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30–31
14  10
 3
MRAS
131211109876543210
CS
SEL
MBA 210
MCAS 9876543210
14  10
 2
MRAS 13121110987654321 0
CS
SEL
MBA 10
MCAS 9876543210
13  10
 3
MRAS 1211109876543210
CS
SEL
MBA 210
MCAS 9876543210
13  10
 2
MRAS 121110987654321 0
CS
SEL
MBA 10
MCAS 9876543210