Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-44 Freescale Semiconductor
Chip select interleaving is supported for the memory controller, and is programmed in
DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects 0 and 1. When
interleaving is enabled, the chip selects being interleaved must use the same size of memory. One extra bit
in the address decode is used for the interleaving to determine which chip select to access.
13 
10  2
MRAS 1211109876543210
MBA 10
MCAS 9876543210
13 
9  2
MRAS 1211109876543210
MBA 10
MCAS 876543210
Table 9-39. DDR2 Address Multiplexing for 16-Bit Data Bus
Row

Col
msb Address from Core Master lsb
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
14 
10 
3
MRAS
131211109876543210
MBA 210
MCAS 9876543210
14 
10 
2
MRAS 131211109876543210
MBA 10
MCAS 9876543210
13 
10 
3
MRAS 1211109876543210
MBA 210
MCAS 9876543210
13 
10 
2
MRAS 1211109876543210
MBA 10
MCAS 9876543210
13 
9 
2
MRAS 1211109876543210
MBA 10
MCAS 876543210
Table 9-38. DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving and Partial Array Self Refresh
Disabled (continued)
Row
¥
Col
msb Address from Core Master lsb
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30–31