Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-42 Freescale Semiconductor
For information on how the DDR2 memory controller handles errors, see Section 9.5.12, “Error
Management.”
9.5.1 DDR SDRAM Interface Operation
The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs with
different sizes can be used in the same system. Fourteen multiplexed address signals and three logical bank
select signals support device densities from 64 Mbits to 2 Gbits. Two chip select (CS) signals support two
banks of DIMM of memory. The DDR SDRAM physical banks can be built from standard memory
modules or directly-attached memory devices. The data path to individual physical banks is 32 bits wide,
40 bits with ECC. The DDR memory controller supports physical bank sizes from 16 Mbytes to
512 Mbytes. The physical banks can be constructed using 8, 16, or 32 memory devices. The memory
technologies supported are 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, and 1 Gbit. Some 2-Gbit devices
are supported depending on the internal device configuration. Nine data qualifier (DQM) signals provide
byte selection for memory accesses.
NOTE
An 8-bit DDR SDRAM device has a DQM signal and eight data signals
(DQ[0:7]). A 16-bit DDR SDRAM device has two DQM signals associated
with specific halves of the 16 data signals (DQ[0:7] and DQ[8:15]).
When ECC is enabled, all memory accesses are performed on double-word boundaries (that is, all DQM
signals are set simultaneously). However, when ECC is disabled, the memory system uses the DQM
signals for byte lane selection.
Table 9-36 shows the DDR memory controller’s relationships between data byte lane0–3, MDM[0:3],
MDQS[0:3], and MDQ[0:31] when DDR SDRAM memories are used with 8 or 16 devices.
9.5.1.1 Supported DDR SDRAM Organizations
Although the DDR memory controller multiplexes row and column address bits onto 14 memory address
signals and 3 logical bank select signals, a physical bank may be implemented with memory devices
requiring fewer than 30 address bits. The physical bank may be configured to provide from 12 to 14 row
address bits, plus 2 to 3 logical bank-select bits and from 8–11 column address bits.
Table 9-37 describe DDR SDRAM device configurations supported by the DDR memory controller.
NOTE
DDR SDRAM is limited to 30 total address bits.
Table 9-36. Byte Lane to Data Relationship
Data Byte Lane Data Bus Mask Data Bus Strobe Data Bus
0 (MSB) MDM[0] MDQS[0] MDQ[0:7]
1 MDM[1] MDQS[1] MDQ[8:15]
2 MDM[2] MDQS[2] MDQ[16:23]
3 MDM[3] MDQS[3] MDQ[24:31]