Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-41
Figure 9-33. Example 64-Mbyte DDR SDRAM Configuration With ECC
CAS
CS
RAS
CKE
CLK
DM
A(11-0)
2Mx8 SDRAM
DQ(7-0)
BA(1-0)
CAS
CS
RAS
CKE
CLK
DM
A(11-0)
2Mx8 SDRAM
DQ(7-0)
BA(1-0)
CAS
CS
RAS
CKE
CLK
DM
A[0-11]
2Mx8 SDRAM
DQ[0-7]
BA[0-1]
CAS
CS
RAS
WE
CKE
CK
DM
A[11:0]
8M
 8 SDRAM
DQ[7:0]
BA[1:0]
0
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
1
2
3
MRAS
MCAS
MWE
MCKE
MCK[0:2]
MCS
[0:1]
MBA[2:0]
MA[13:0]
MDQ[0:31]
MDM[0:3],
To all SDRAM
Devices in
Common
Memory Data Bus and Strobes
Two Banks of 8M
 32 (32 Mbytes each)
MDQS[0]
MDQS
MDQS[0:3]
3. Buffering may be needed if large memory arrays are used.
2. Each of the MCS
[0:1] signals correspond with a separate physical bank of memory.
1. All signals are connected in common (in parallel) except for MCS
[0:1], MCK[0:2], MCK[0:2], MDM[0:3], MDM[8],
DDR
Controller
MCK[0:2]
MDQS[3]
CAS
CS
RAS
CKE
CLK
DM
A(11-0)
2Mx8 SDRAM
DQ(7-0)
BA(1-0)
CAS
CS
RAS
CKE
CLK
DM
A(11-0)
2Mx8 SDRAM
DQ(7-0)
BA(1-0)
CAS
CS
RAS
CKE
CLK
DM
A[0-11]
2Mx8 SDRAM
DQ[0-7]
BA[0-1]
CAS
CS
RAS
WE
CKE
CK
DM
A[11:0]
8M
 8 SDRAM
DQ[7:0]
BA[1:0]
MDQS
1
2
3
0
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
MDQS[0]
MDQS[3]
MDM[8]
CAS
CS
RAS
CKE
CK
DM
A[11:0]
8M
 8 SDRAM
DQ[7:0]
BA[1:0]
ECC[0:7]
MDQS[8]
MDQS
CAS
CS
RAS
CKE
CK
DM
A[11:0]
8M
 8 SDRAM
DQ[7:0]
BA[1:0]
8
ECC[0:7]
MDQS[8]
MDQS
WE
WE
8
Bank 0
Bank 1
MDQS[8]
ECC[0:7]
and the data bus signals.