Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-39
Figure 9-31 shows an example DDR SDRAM configuration with four logical banks.
Figure 9-31. Typical Dual Data Rate SDRAM Internal Organization
Figure 9-32 shows some typical signal connections.
Figure 9-32. Typical DDR SDRAM Interface Signals
Figure 9-33 shows an example DDR SDRAM configuration with two physical banks each comprised of
four 8M  8 DDR modules for a total of 64 Mbytes of system memory. One of the nine modules is used
for the memory’s ECC checking function. Certain address and control lines may require buffering.
Analysis of the device’s AC timing specifications, desired memory operating frequency, capacitive loads,
Logical
Bank 0
Logical
Bank 1
Logical
Bank 2
Logical
Bank 3
MUX, MASK,
Read Data Latch
Data-Out Registers Data-In Registers
Data Bus
ADDR
COMMAND:
DQM
BA1,BA0
CKE, MCK, MCK
MCS, MRAS, MCAS, MWE
Control
SDRAM
A[12:0]
Write Enable
DQ[7:0]
DQS
64M x 1 Byte
CK
Command
Bus
512 Mbit
BA[1:0]
DATA
DATA
8
ADDR
MRAS
MCAS
MWE
MCS
DM
CKE
MCK
MCK
13
2
‘SUB’
BANK ADDR
STROBE