Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-38 Freescale Semiconductor
9.5 Functional Description
The DDR SDRAM controller controls processor and I/O interactions with system memory. It provides
support for JEDEC-compliant DDR2 SDRAM. The memory system allows a wide range of memory
devices to be mapped to any arbitrary chip select, and support is provided for registered DIMMs and
unbuffered DIMMs. However, registered DIMMs cannot be mixed with unbuffered DIMMs.
Figure 9-1 is a high-level block diagram of the DDR memory controller. Requests are received from the
internal mastering device and the address is decoded to generate the physical bank, logical bank, row, and
column addresses. The transaction is compared with values in the row open table to determine if the
address maps to an open page. If the transaction does not map to an open page, an active command is
issued.
The memory interface supports as many as two physical banks of 16-/24-/32-/40-bit wide memory. Bank
sizes up to 512 Mbytes are supported, providing up to a maximum of 1 Gbytes of DDR main memory.
Programmable parameters allow for a variety of memory organizations and timings. Optional error
checking and correcting (ECC) protection is provided for the DDR SDRAM data bus. Using ECC, the
DDR memory controller detects and corrects all single-bit errors within the 32-bit data bus, detects all
double-bit errors within the 32-bit data bus, and detects all errors within a nibble. The controller allows as
many as 16 pages to be open simultaneously. The amount of time (in clock cycles) the pages remain open
is programmable with DDR_SDRAM_INTERVAL[BSTOPRE].
Read and write accesses to memory are burst oriented; accesses start at a selected location and continue
for a programmed number of higher locations (4) in a programmed sequence. Accesses to closed pages
start with the registration of an ACTIVE command followed by a READ or WRITE. (Accessing open
pages does not require an ACTIVE command.) The address bits registered coincident with the activate
command specifies the logical bank and row to be accessed. The address coincident with the READ or
WRITE command specifies the logical bank and starting column for the burst access.
The data interface is source synchronous, meaning whatever sources the data also provides a clocking
signal to synchronize data reception. These bidirectional data strobes (MDQS[0:3]) are inputs to the
controller during reads and outputs during writes. The DDR SDRAM specification requires the data strobe
signals to be centered within the data tenure during writes and to be offset by the controller to the center
of the data tenure during reads. This delay is implemented in the controller for both reads and writes.
When ECC is enabled, 1 clock cycle is added to the read path to check ECC and correct single-bit errors.
ECC generation does not add a cycle to the write path.
The address and command interface is also source synchronous, although 1/8 cycle adjustments are
provided for adjusting the clock alignment.