Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-37
9.4.1.28 Memory Error Address Capture (CAPTURE_ADDRESS)
The memory error address capture register, shown in Figure 9-29, holds the 32 lsbs of a transaction when
a DDR ECC error is detected.
Table 9-34 describes the CAPTURE_ADDRESS fields.
9.4.1.29 Single-Bit ECC Memory Error Management (ERR_SBE)
The single-bit ECC memory error management register, shown in Figure 9-30, stores the threshold value
for reporting single-bit errors and the number of single-bit errors counted since the last error report. When
the counter field reaches the threshold, it wraps back to the reset value (0). If necessary, software must clear
the counter after it has managed the error.
Table 9-35 describes the ERR_SBE fields.
Offset 0xE50 Access: Read/Write
0 31
R
CADDR
W
Reset All zeros
Figure 9-29. Memory Error Address Capture Register (CAPTURE_ADDRESS)
Table 9-34. CAPTURE_ADDRESS Field Descriptions
Bits Name Description
0–31 CADDR Captured address. Captures the 32 lsbs of the transaction address when an error is detected.
Offset 0xE58 Access: Read/Write
0 7 8 1516 2324 31
R
— SBET — SBEC
W
Reset All zeros
Figure 9-30. Single-Bit ECC Memory Error Management Register (ERR_SBE)
Table 9-35. ERR_SBE Field Descriptions
Bits Name Description
0–7 — Reserved
8–15 SBET Single-bit error threshold. Establishes the number of single-bit errors that must be detected before an error
condition is reported. As a special case, setting this to zero means error threshold is set to 256.
16–23 — Reserved
24–31 SBEC Single-bit error counter. Indicates the number of single-bit errors detected and corrected since the last error
report. If single-bit error reporting is enabled, an error is reported and an interrupt is generated when this value
equals SBET. SBEC is automatically cleared when the threshold value is reached.