Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-36 Freescale Semiconductor
9.4.1.27 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES)
The memory error attributes capture register, shown in Figure 9-28, sets attributes for errors including
type, size, source, and others.
Table 9-33 describes the CAPTURE_ATTRIBUTES fields.
Offset 0xE4C Access: Read/Write
0 1 3 4 5 7 8 1011 151617 181920 30 31
R
— BNUM — TSIZ — TSRC — TTYP — VLD
W
Reset All zeros
Figure 9-28. Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)
Table 9-33. CAPTURE_ATTRIBUTES Field Descriptions
Bits Name Description
0—Reserved
1–3 BNUM Data beat number. Captures the doubleword number for the detected error. Relevant only for ECC errors.
4—Reserved
5–7 TSIZ Transaction size for the error. Captures the transaction size in double words.
000 4 double words
001 1 double word
010 2 double words
011 3 double words
Others Reserved
8–10 — Reserved
11–15 TSRC Transaction source for the error
00000 e300 core data transaction
00001 Reserved
00010 e300 core instruction fetch
00011 Reserved
00100 eTSEC1
00101 eTSEC2
00110 Reserved
00111 USB
01000 Reserved
01001 I
2
C (boot sequencer)
01010 JTAG
01011 Reserved
01100 eSDHC
01101–11100 Reserved
11101 PCI Express
11110 Reserved
11111 DMA
16–17 — Reserved
18–19 TTYP Transaction type for the error.
00 Reserved
01 Write
10 Read
11 Read-modify-write
20–30 — Reserved
31 VLD Valid. Set as soon as valid information is captured in the error capture registers.