Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-34 Freescale Semiconductor
9.4.1.25 Memory Error Disable (ERR_DISABLE)
The memory error disable register, shown in Figure 9-26, allows selective disabling of the DDR
controller’s error detection circuitry. Disabled errors are not detected or reported.
Table 9-31 describes the ERR_DISABLE fields.
24 ACE Automatic calibration error. This bit is cleared by software writing a 1.
0 An automatic calibration error has not been detected.
1 An automatic calibration error has been detected.
25–27 — Reserved
28 MBE Multiple-bit error. This bit is cleared by software writing a 1.
0 A multiple-bit error has not been detected.
1 A multiple-bit error has been detected.
29 SBE Single-bit ECC error. This bit is cleared by software writing a 1.
0 The number of single-bit ECC errors detected has not crossed the threshold set in ERR_SBE[SBET].
1 The number of single-bit ECC errors detected crossed the threshold set in ERR_SBE[SBET].
30 — Reserved
31 MSE Memory select error. This bit is cleared by software writing a 1.
0 A memory select error has not been detected.
1 A memory select error has been detected.
Offset 0xE44 Access: Read/Write
0 23 24 25 27 28 29 30 31
R
— ACED — MBED SBED — MSED
W
Reset All zeros
Figure 9-26. Memory Error Disable Register (ERR_DISABLE)
Table 9-31. ERR_DISABLE Field Descriptions
Bits Name Description
0–23 — Reserved
24 ACED Automatic calibration error disable
0 Automatic calibration errors are enabled.
1 Automatic calibration errors are disabled.
25–27 — Reserved
28 MBED Multiple-bit ECC error disable
0 Multiple-bit ECC errors are detected if DDR_SDRAM_CFG[ECC_EN] is set. They are reported if
ERR_INT_EN[MBEE] is set.
1 Multiple-bit ECC errors are not detected or reported.
29 SBED Single-bit ECC error disable
0 Single-bit ECC errors are enabled.
1 Single-bit ECC errors are disabled.
Table 9-30. ERR_DETECT Field Descriptions (continued)
Bits Name Description