Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-31
9.4.1.19 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)
The memory data path error injection mask low register is shown in Figure 9-20.
Table 9-25 describes the DATA_ERR_INJECT_LO fields.
9.4.1.20 Memory Data Path Error Injection Mask ECC (ERR_INJECT)
The memory data path error injection mask ECC register, shown in Figure 9-21, sets the ECC mask,
enables errors to be written to ECC memory, and allows the ECC byte to mirror the most significant data
byte.
Table 9-26 describes the ERR_INJECT fields.
Offset 0xE04 Access: Read/Write
0 31
R
EIML
W
Reset All zeros
Figure 9-20. Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)
Table 9-25. DATA_ERR_INJECT_LO Field Descriptions
Bits Name Description
0–31 EIML Error injection mask low data path. Used to test ECC by forcing errors on the low word of the data path. Setting
a bit causes the corresponding data path bit to be inverted on memory bus writes.
Offset 0xE08 Access: Read/Write
0 21 22 23 24 31
R
— EMB EIEN EEIM
W
Reset All zeros
Figure 9-21. Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)
Table 9-26. ERR_INJECT Field Descriptions
Bits Name Description
0–21 — Reserved
22 EMB ECC mirror byte
0 Mirror byte functionality disabled.
1 Mirror the most significant data path byte onto the ECC byte.
23 EIEN Error injection enable
0 Error injection disabled.
1 Error injection enabled. This applies to the data mask bits, the ECC mask bits, and the ECC mirror bit. Note
that error injection should not be enabled until the memory controller has been enabled through
DDR_SDRAM_CFG[MEM_EN].
24–31 EEIM ECC error injection mask. Setting a mask bit causes the corresponding ECC bit to be inverted on memory
bus writes.