Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-30 Freescale Semiconductor
9.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2)
The DDR IP block revision 2 register, shown in Figure 9-18, provides read-only fields with the IP block
integration and configuration options.
Table 9-23 describes the DDR_IP_REV2 fields.
9.4.1.18 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)
The memory data path error injection mask high register is shown in Figure 9-19.
Table 9-24 describes the DATA_ERR_INJECT_HI fields.
Offset 0xBFC Access: Read Only
0 7 8 1516 2324 31
R
—
IP_INT
—
IP_CFG
W
Reset00000000n nnnnnnn00000000nnnnnnnn
Figure 9-18. DDR IP Block Revision 2 (DDR_IP_REV2)
Table 9-23. DDR_IP_REV2 Field Descriptions
Bits Name Description
0–7 — Reserved
8–15 IP_INT IP block integration options. This is currently set to 0x0000.
16–23 — Reserved
24–31 IP_CFG IP block configuration options. This is currently set to 0x82.
Offset 0xE00 Access: Read/Write
0 31
R
EIMH
W
Reset All zeros
Figure 9-19. Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI)
Table 9-24. DATA_ERR_INJECT_HI Field Descriptions
Bits Name Description
0–31 EIMH Error injection mask high data path. Used to test ECC by forcing errors on the high word of the data path.
Setting a bit causes the corresponding data path bit to be inverted on memory bus writes.