Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-29
9.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)
The DDR SDRAM initialization address register, shown in Figure 9-16, provides the address that is used
for the automatic CAS to preamble calibration after POR.
Table 9-21 describes the DDR_INIT_ADDR fields.
9.4.1.16 DDR IP Block Revision 1 (DDR_IP_REV1)
The DDR IP block revision 1 register, shown in Figure 9-17, provides read-only fields with the IP block
ID, along with major and minor revision information.
Table 9-22 describes the DDR_IP_REV1 fields.
Offset 0x148 Access: Read/Write
0 31
R
INIT_ADDR
W
Reset All zeros
Figure 9-16. DDR Initialization Address Configuration Register (DDR_INIT_ADDR)
Table 9-21. DDR_INIT_ADDR Field Descriptions
Bits Name Description
0–31 INIT_ADDR Initialization address. Represents the address that is used for the automatic CAS to preamble calibration
at POR.
Offset 0xBF8 Access: Read Only
01516232431
RIP_ID IP_MJIP_MN
W
Reset n
1
1
For reset values, see Ta bl e 9-2 2.
nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn
Figure 9-17. DDR IP Block Revision 1 (DDR_IP_REV1)
Table 9-22. DDR_IP_REV1 Field Descriptions
Bits Name Description
0–15 IP_ID IP block ID. For the DDR controller, this value is 0x0002.
16–23 IP_MJ Major revision. This is currently set to 0x02.
24–31 IP_MN Minor revision. This is currently set to 0x01.