Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-28 Freescale Semiconductor
9.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT)
The DDR SDRAM data initialization register, shown in Figure 9-14, provides the value that is used to
initialize memory if DDR_SDRAM_CFG2[D_INIT] is set.
Table 9-19 describes the DDR_DATA_INIT fields.
9.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
The DDR SDRAM clock control configuration register, shown in Figure 9-15, provides a 1/4-cycle clock
adjustment.
Table 9-20 describes the DDR_SDRAM_CLK_CNTL fields.
Offset 0x128 Access: Read/Write
0 31
R
INIT_VALUE
W
Reset All zeros
Figure 9-14. DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)
Table 9-19. DDR_DATA_INIT Field Descriptions
Bits Name Description
0–31 INIT_VALUE Initialization value. Represents the value that DRAM is initialized with if DDR_SDRAM_CFG2[D_INIT]
is set.
Offset 0x130 Access: Read/Write
045789 31
R
— CLK_ADJUST — —
W
Reset00000 0 1 0 000000000000000000000000
Figure 9-15. DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)
Table 9-20. DDR_SDRAM_CLK_CNTL Field Descriptions
Bits Name Description
0–4 — Reserved
5–7 CLK_ADJUST Clock adjust.
000 Clock is launched aligned with address/command
001 Clock is launched 1/4 applied cycle after address/command
010 Clock is launched 1/2 applied cycle after address/command
011 Clock is launched 3/4 applied cycle after address/command
100 Clock is launched 1 applied cycle after address/command
101–111Reserved
8 — Reserved, should be cleared.
9–31 — Reserved