Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-27
9.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)
The DDR SDRAM interval configuration register, shown in Figure 9-13, sets the number of DRAM clock
cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM cycles that
a page is maintained after it is accessed is provided here.
Table 9-18 describes the DDR_SDRAM_INTERVAL fields.
CS_SEL Chooses chip select (CS) —
MD_SEL Select mode register.
See Ta ble 9 -1 6.
— Selects logical bank —
MD_VALUE Value written to mode
register
— Only bit five is significant.
See Table 9- 16.
—
CKE_CNTL 0 0 0 See Ta bl e 9- 16 .
Offset 0x124 Access: Read/Write
0 15161718 31
R
REFINT — BSTOPRE
W
Reset All zeros
Figure 9-13. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
Table 9-18. DDR_SDRAM_INTERVAL Field Descriptions
Bits Name Description
0–15 REFINT Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical bank
during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface
clock frequency. Refreshes are not issued when the REFINT is set to all 0s.
16–17 — Reserved
18–31 BSTOPRE Precharge interval. Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM
access. If BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands
rather than operating in page mode. This is called global auto-precharge mode.
Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields (continued)
Field Mode Register Set Refresh Precharge
Clock Enable Signals
Control