Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-25
9.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
The DDR SDRAM mode control register, shown in Figure 9-12, allows the user to carry out the following
tasks:
• Issue a mode register set command to a particular chip select
• Issue an immediate refresh to a particular chip select
• Issue an immediate precharge or precharge all command to a particular chip select
• Force the CKE signals to a specific value
Table 9-16 describes the fields of this register. Table 9-17 shows the user how to set the fields of this
register to accomplish the above tasks.
Table 9-16 describes the DDR_SDRAM_MD_CNTL fields.
NOTE
Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; only
one of these fields can be set at a time.
Offset 0x120 Access: Read/Write
0123457 8 9 1011 12 1516 31
R
MD_EN — CS_SEL — MD_SEL SET_REF SET_PRE CKE_CNTL — MD_VALUE
W
Reset All zeros
Figure 9-12. DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions
Bits Name Description
0 MD_EN Mode enable. Setting this bit specifies that valid data in MD_VALUE is ready to be written to DRAM as one
of the following commands:
• MODE REGISTER SET
• EXTENDED MODE REGISTER SET
• EXTENDED MODE REGISTER SET 2
• EXTENDED MODE REGISTER SET 3
The specific command to be executed is selected by setting MD_SEL. In addition, the chip select must be
chosen by setting CS_SEL. MD_EN is set by software and cleared by hardware once the command has
been issued.
0 Indicates that no mode register set command needs to be issued.
1 Indicates that valid data contained in the register is ready to be issued as a mode register set command.
1 — Reserved
2–3 CS_SEL Select chip select. Specifies the chip select that is driven active due to any command forced by software in
DDR_SDRAM_MD_CNTL.
00 Chip select 0 is active
01 Chip select 1 is active
10 Reserved
11 Reserved
4 — Reserved