Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-23
9.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)
The DDR SDRAM mode configuration register, shown in Figure 9-10, sets the values loaded into the
DDR’s mode registers.
16–19 NUM_PR Number of posted refreshes. This determines how many posted refreshes, if any, can be issued at
one time. Note that if posted refreshes are used, then this field, along with
DDR_SDRAM_INTERVAL[REFINT], must be programmed such that the maximum t
ras
specification
cannot be violated.
0000 Reserved
0001 1 refresh is issued at a time
0010 2 refreshes is issued at a time
0011 3 refreshes is issued at a time
...
1000 8 refreshes is issued at a time
1001–1111 Reserved
20–26 — Reserved, should be cleared.
27 D_INIT DRAM data initialization. This bit is set by software, and it is cleared by hardware. If software sets this
bit before the memory controller is enabled, the controller automatically initializes DRAM after it is
enabled. This bit is automatically cleared by hardware once the initialization is completed. This data
initialization bit should only be set when the controller is idle.
0 There is not data initialization in progress, and no data initialization is scheduled
1 The memory controller initializes memory once it is enabled. This bit remains asserted until the
initialization is complete. The value in DDR_DATA_INIT register is used to initialize memory.
28–31 — Reserved
Offset 0x118 Access: Read/Write
0151631
R
ESDMODE SDMODE
W
Reset All zeros
Figure 9-10. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)
Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions (continued)
Bits Name Description