Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-22 Freescale Semiconductor
9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)
The DDR SDRAM control configuration register 2, shown in Figure 9-9, provides more control
configuration for the DDR controller.
Table 9-13 describes the DDR_SDRAM_CFG_2 fields.
Offset 0x114 Access: Read/Write
01 2 3456 8 9 1011 15
R
FRC_SR — DLL_RST_DIS — DQS_CFG — ODT_CFG —
W
Reset All zeros
16 19 20 26 27 28 31
R
NUM_PR — D_INIT —
W
Reset All zeros
Figure 9-9. DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)
Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions
Bits Name Description
0 FRC_SR Force self refresh
0 DDR controller operates in normal mode.
1 DDR controller enters self-refresh mode.
1 — Reserved. Should be cleared.
2 DLL_RST_DIS DLL reset disable. The DDR controller typically issues a DLL reset to the DRAMs when exiting self
refresh. However, this function may be disabled by setting this bit during initialization.
0 DDR controller issues a DLL reset to the DRAMs when exiting self refresh.
1 DDR controller does not issue a DLL reset to the DRAMs when exiting self refresh.
3—Reserved
4–5 DQS_CFG DQS configuration
00 Only true DQS signals are used.
01 Reserved
10 Reserved
11 Reserved
6–8 — Reserved
9–10 ODT_CFG ODT configuration. This field defines how ODT is driven to the on-chip IOs. See Section 5.2.2.9,
“DDR Control Driver Register (DDRCDR),” which defines the termination value that is used.
00 Never assert ODT to internal IOs
01 Assert ODT to internal IOs only during writes to DRAM
10 Assert ODT to internal IOs only during reads to DRAM
11 Always keep ODT asserted to internal IOs
11–15 — Reserved.