Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-21
17–23 BA_INTLV_CTL Bank (chip select) interleaving control. Set this field only if you wish to use bank interleaving.
(All unlisted field values are reserved.)
0000000No external memory banks are interleaved
1000000External memory banks 0 and 1 are interleaved
24–26 — Reserved
27 PCHB8 Precharge bit 8 enable.
0 MA[10] is used to indicate the auto-precharge and precharge all commands.
1 MA[8] is used to indicate the auto-precharge and precharge all commands.
28 HSE Global half-strength override
S
Sets I/O driver impedance to half strength. This impedance is used by the address/command, data,
and clock impedance values, but only if automatic hardware calibration is disabled and the
corresponding group's software override is disabled in the DDR control driver register(s) described
in Section 5.2.2.9, “DDR Control Driver Register (DDRCDR).” This bit should be cleared if using
automatic hardware calibration.
0 I/O driver impedance is configured to full strength.
1 I/O driver impedance is configured to half strength.
29 — Reserved
30 MEM_HALT DDR memory controller halt. When this bit is set, the memory controller does not accept any new
data read/write transactions to DDR SDRAM until the bit is cleared again. This can be used when
bypassing initialization and forcing MODE REGISTER SET commands through software.
0 DDR controller accepts new transactions.
1 DDR controller finishes any remaining transactions, and then it remains halted until this bit is
cleared by software.
31 BI Bypass initialization
0 DDR controller cycles through initialization routine based on SDRAM_TYPE
1 Initialization routine is bypassed. Software is responsible for initializing memory through
DDR_SDRAM_MODE2 register. If software is initializing memory, then the MEM_HALT bit can be
set to prevent the DDR controller from issuing transactions during the initialization sequence.
Note that the DDR controller does not issue a DLL reset to the DRAMs when bypassing the
initialization routine, regardless of the value of DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL
reset is required, then the controller should be forced to enter and exit self refresh after the
controller is enabled.
See Section 9.4.1.15, “DDR Initialization Address (DDR_INIT_ADDR),” for details on avoiding ECC
errors in this mode.
Table 9-12. DDR_SDRAM_CFG Field Descriptions (continued)
Bits Name Description